Low-Power Digital Circuit
Low-Power Digital Circuit Design
Here are the results of our research on low-power digital circuits:
1) Near-Threshold Circuit Design
Variation-Tolerant Digital Circuit Design
Abstract-
Related Publications
Sungju Ryu, Jongeun Koo, Wook Kim, Yonghwan Kim, Jae-Joon Kim, "Variation-Tolerant Elastic Clock Scheme for Low-Voltage Operations," IEEE Journal of Solid-State Circuits (JSSC), Jul. 2021.
Sungju Ryu, Jongeun Koo, Jae-Joon Kim, “Low Design Overhead Timing Error Correction Scheme for Elastic Clock Methodology,” IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), Jul. 2017. (BK21+ Computer Science분야 우수국제학술대회)
Jongeun Koo, Eunwoo Song, Eunhyeok Park, Dongyoung Kim, Junki Park, Sungju Ryu, Sungjoo Yoo, Jae-Joon Kim, “Area-Efficient One-Cycle Correction Scheme for Timing Errors in Flip-Flop Based Pipelines,” IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov. 2016.
2) Efficient MAC Design for Machine Learning Applications
Feedforward-Cutset-Free MAC
Abstract-
Related Publications
Sungju Ryu, Naebeom Park, Jae-Joon Kim, “Feedforward-Cutset-Free Pipelined Multiply-Accumulate Unit for the Machine Learning Accelerator,” IEEE Transactions on VLSI Systems (TVLSI), Vol. 27, No. 1, pp 138-146, Jan. 2019.
