Publications
2025
Sangyeon Kim, Hyunmin Kim, Sungju Ryu, "Thanos: Energy-Efficient Keyword Spotting Processor with Hybrid Time-Feature-Frequency-Domain Zero-Skipping," Design Automation and Test in Europe (DATE), Mar. 2025. (BK21/정보과학회 인정 Computer Science분야 우수국제학술대회)
Thanh-Dat Nguyen, Sungju Ryu*, Ik-Joon Chang*, "TRIO-TCAM: An Area and Energy-Efficient Triple-State-in-Cell Ternary Content-Addressable Memory Architecture," IEEE Access, Accepted for publication. (*: Co-corresponding Authors)
Sungju Ryu, Jae-Joon Kim, "High-Performance Sparsity-Aware NPU with Reconfigurable Comparator-Multiplier Architecture," Journal of Semiconductor Technology and Science (JSTS), Accepted for publication.
2024
Hyunmin Kim, Sungju Ryu, "NexusCIM: High-Throughput Multi-CIM Array Architecture with C-Mesh NoC and Hub Cores," IEEE International Conference on Computer Design (ICCD), Nov. 2024. (BK21/정보과학회 인정 Computer Science분야 우수국제학술대회)
Sungju Ryu, Jaeyong Jang, Youngtaek Oh, Jae-Joon Kim, "Mobileware: Distributed Architecture with Channel Stationary Dataflow for MobileNet Acceleration," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Sep. 2024.
Yeonggeon Kim, Hyunmin Kim, Sungju Ryu, "Statues: Energy-Efficient Video Object Detection on Edge Security Devices with Computational Skipping," ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), Aug. 2024. (BK21/정보과학회 인정 Computer Science분야 우수국제학술대회)
Sungju Ryu, "Resource Analysis on FPGA for Functional Verification of Digital SRAM PIM," Journal of Semiconductor Technology and Science (JSTS), Jun. 2024.
2023
Gwanghwi Seo, Sungju Ryu, "Area-Efficient AdderNet Hardware Accelerator with Merged Adder Tree Structure," IEICE Electronics Express, Dec. 2023.
Sungju Ryu*, Youngtaek Oh*, Jae-Joon Kim, "Binaryware: A High-Performance Digital Hardware Accelerator for Binary Neural Networks," IEEE Transactions on VLSI Systems (TVLSI), Dec. 2023. (*: Equally contributed authors)
Hyunmin Kim, Sungju Ryu, "Teleport: A High-Performance ShiftNet Hardware Accelerator with Fused Layer Computation," ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), Aug. 2023. (BK21/정보과학회 인정 Computer Science분야 우수국제학술대회)
2022
Sungju Ryu, "Review and Analysis of Variable Bit-Precision MAC Microarchitectures for Energy-Efficient AI Computation,"Journal of Semiconductor Technology and Science (JSTS), Oct. 2022.
Sungju Ryu, Hyungjun Kim, Wooseok Yi, Eunhwan Kim, Yulhwa Kim, Taesu Kim, Jae-Joon Kim, "BitBlade: Energy-Efficient Variable Bit-Precision Hardware Accelerator for Quantized Neural Networks," IEEE Journal of Solid-State Circuits (JSSC), Jun. 2022.
2021
Sungju Ryu, Youngtaek Oh, Jae-Joon Kim, "Mobileware: A High-Performance MobileNet Accelerator with Channel Stationary Dataflow," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 2021. (BK21/정보과학회 인정 Computer Science분야 우수국제학술대회)
Sungju Ryu, Jongeun Koo, Wook Kim, Yonghwan Kim, Jae-Joon Kim, "Variation-Tolerant Elastic Clock Scheme for Low-Voltage Operations," IEEE Journal of Solid-State Circuits (JSSC), Jul. 2021.
Naebeom Park, Sungju Ryu, Jaeha Kung, Jae-Joon Kim, "High-Throughput Near-Memory Processing on CNNs with 3D HBM-like Memory," ACM Transactions on Design Automation of Electronic Systems (TODAES), Jun. 2021.
Sungju Ryu, Youngtaek Oh, Taesu Kim, Daehyun Ahn, Jae-Joon Kim, "SPRITE: Sparsity-Aware Neural Processing Unit with Constant Probability of Index-Matching," Design Automation and Test in Europe (DATE), Feb. 2021. (BK21/정보과학회 인정 Computer Science분야 우수국제학술대회)
Before 2021
Hyungjun Kim, Yulhwa Kim, Sungju Ryu, Jae-Joon Kim, "Algorithm-Hardware Co-Design for In-Memory Neural Network Computing with Minimal Peripheral Circuit Overhead," ACM/IEEE Design Automation Conference (DAC), Jul. 2020. (BK21/정보과학회 인정 Computer Science분야 우수국제학술대회)
Jongeun Koo, Jinseok Kim, Sungju Ryu, Chulsoo Kim, Jae-Joon Kim, “Area-Efficient Transposable Crossbar Synapse Memory Using 6T SRAM Bit Cell for Fast Online Learning of Neuromorphic Processors,” Journal of Semiconductor Technology and Science (JSTS), Apr. 2020.
Sungju Ryu, Hyungjun Kim, Wooseok Yi, Jongeun Koo, Eunhwan Kim, Yulhwa Kim, Taesu Kim, Jae-Joon Kim, "A 44.1TOPS/W Precision-Scalable Accelerator for Quantized Neural Networks in 28nm CMOS," IEEE Custom Integrated Circuits Conference (CICC), Mar. 2020.
Jongeun Koo, Eunhwan Kim, Seunghyun Yoo, Taesu Kim, Sungju Ryu, Jae-Joon Kim, “Configurable BCAM/TCAM Based on 6T SRAM Bit Cell and Enhanced Match Line Clamping,” IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov. 2019.
Sungju Ryu, Hyungjun Kim, Wooseok Yi, Jae-Joon Kim, “BitBlade: Area and Energy-Efficient Precision-Scalable Neural Network Accelerator with Bitwise Summation,” ACM/IEEE Design Automation Conference (DAC), Jun. 2019. (BK21/정보과학회 인정 Computer Science분야 우수국제학술대회)
Jongeun Koo, Eunhyeok Park, Dongyoung Kim, Junki Park, Sungju Ryu, Sungjoo Yoo, Jae-Joon Kim, "Low-Overhead, One-Cycle Timing-Error Detection and Correction Technique for Flip-Flop Based Pipelines," IEICE Electronics Express, May. 2019.
Jongeun Koo, Jinseok Kim, Sungju Ryu, Chulsoo Kim, Jae-Joon Kim, “Area-Efficient Transposable 6T SRAM for Fast Online Learning in Neuromorphic Processors,” IEEE Custom Integrated Circuits Conference (CICC), Apr. 2019.
Sungju Ryu, Naebeom Park, Jae-Joon Kim, “Feedforward-Cutset-Free Pipelined Multiply-Accumulate Unit for the Machine Learning Accelerator,” IEEE Transactions on VLSI Systems (TVLSI), Vol. 27, No. 1, pp 138-146, Jan. 2019.
Sungju Ryu, Jongeun Koo, Jae-Joon Kim, “Low Design Overhead Timing Error Correction Scheme for Elastic Clock Methodology,” IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), Jul. 2017. (BK21/정보과학회 인정 Computer Science분야 우수국제학술대회)
Jongeun Koo, Eunwoo Song, Eunhyeok Park, Dongyoung Kim, Junki Park, Sungju Ryu, Sungjoo Yoo, Jae-Joon Kim, “Area-Efficient One-Cycle Correction Scheme for Timing Errors in Flip-Flop Based Pipelines,” IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov. 2016.